What's New in Release 16.2






 

The new technology helps deliver shorter, more predictable design cycles for PCB designs. With significant improvements for designers using high-density interconnect (HDI), the technology will be of particular value to customers in the high-end consumer electronics market, as well as those in segments such as computing and networking where users are seeking a constraint-driven HDI design flow.

New technology introduced in Allegro PCB Editor for HDI designs includes new objects, an extensive set of new rules for micro-vias, an enhanced via-transition use model, and changes to the entire PCB design flow to enable a comprehensive constraint-driven HDI design flow. Design partitioning has been enhanced with new capabilities for partitioning the design horizontally and adding soft boundaries to allow users to work in parallel more efficiently, further shortening the design cycle.

Click here for the PDF 16.2 Release presentation or catch the highlights below

Cadence Allegro Design Entry HDL New Features Cadence Allegro Design Entry CIS features Cadence Allegro PCB Editor features Cadence Allegro PCB SI features

Cadence Allegro Design Entry HDL


Allegro Design Entry HDL is a design environment that supports behavioural and structural design descriptions captured in text and graphics. It includes block-editing functions for quick architectural design. This schematic-based design entry solution is fully integrated within the Allegro platform.

Automatic Table of Contents Generator - In many of the designs you create, the first sheet of the schematic contains the table of contents (TOC). A TOC provides a quick view of the design contents in single or multiple pages. Allegro DE-HDL 16.2 provides functionality for creating and automatically updating TOC with design information. This feature replaces any indigenous solutions that you might have been using until now. The automatic TOC generator feature saves you design time, as it does not require any manual validation.

Cross-References as Links – The Cross-Reference (CRefer) utility is used for verification and debugging of designs by following a signal's path throughout the design. CRefer traces out the flow of a signal all over the design and by annotating some properties on the schematic makes the signal navigation simpler. In the 16.2 release, these property values are converted to hyperlinks. You can now click these links and navigate to the location as specified in the property value.

Physical and Spacing Constraints - The 16.2 release allows you to connect the Allegro Constraint Manager to Allegro DE-HDL. You can create, view, edit, and assign physical and spacing constraints to a group of nets or directly to nets in addition to electrical constraints.

Physical Constraints in Allegro Design Entry HDLPhysical constrains in Allegro Design Entry HDL (Click for larger image)

Show Unconnected Pins - Allegro DE-HDL now provides a method to quickly identify all the components which have unconnected pins.

Layout-Driven RF Design - In release 16.2, a layout-driven RF PCB Import flow has been integrated with the traditional import physical flow. If your designs contain RF circuitry, you can synchronize the RF circuitry in the schematic with the layout.