Efficient definition and constraint management

Allegro Design Authoring enables system designers to create design intent quickly. It provides the critical first step in PCB design definition and constraint management that keeps the design flow on track.

Systems companies looking to create new products at the lowest possible cost need a way to author their designs with ease in a shorter, more predictable design cycle. With the increased use of new standards-based interfaces, architectures, and implementation approaches, hardware designers require a design authoring solution that scales with their evolving technology and methodology needs. Cadence® Allegro® Design Authoring is a scalable and easy-to-use solution for fast design intent creation (connectivity plus high-speed constraints) using either schematics or a spreadsheet-like interface.

Cadence® Allegro® Design Authoring is an enterprise-enabled design creation solution that allows schematic designers to create complex designs quickly and efficiently. It provides advanced productivity features such as reuse of previous schematic designs as blocks or sheets—partially or completely.

Oriented around team-based development, Allegro Design Authoring allows schematic designers and layout engineers to work in parallel. Users can capture physical and electrical constraints and assign design rules with the embedded Allegro Constraint Manager. Integrated with Allegro AMS Simulator for analog and digital simulation and SI analysis, Design Authoring also offers multiple options for FPGA integration.

Features/Benefits

• Provides schematic and HDL/Verilog® design input
• Assigns and manages high-speed design rules
• Supports net classes, buses, extended nets, and differential pairs
• Eliminates rework with powerful library creation and management
• Allows synchronization of logical and physical design
• Enables multi-user parallel development with systematic version control
• Integrates smoothly into pre-layout simulation and signal analysis
• Supports customizable user interface and enterprise deployment