Constraint Driven HDI Design Flow

 

 





Customers in the high-end consumer electronics market place, mobile phone makers, GPS navigation system makers have been dealing with miniaturization for quite some time now and have been using build-up process to fabricate PCBs. With smaller and smaller pin pitch BGAs being introduced -- with 0.8 mm pin pitch or lower at 0.65, 0.5, 0.4 mm pin pitches -- there is no way to drill a through hole via through the BGAs.

While miniaturization is not necessarily the primary objective for customers in many other market segments (such as computing and networking), they are being forced to use build-up technology for fanning out a BGA -- particularly if the BGA has 3 or 4 rows of pins on each side. For cost reasons most customers tend to use 2 build-up layers on each side of the PCB and have the traditional rigid PCB as the core.

For customers in most, if not all, market segments having a Constraint Driven PCB design flow is a requirement. It is well known that over the past 8-10 years the number of nets that have high-speed requirements has been growing.

ALIVH Complet Build-Up diagram

Diagram of ALIVH Complete Build-up

Diagram of Core + Build-up Hybrid approch
Diagram of Core + Build-up Hybrid approch


High density interconnects (HDI) are defined as substrates or boards with a higher wiring density per unit area than conventional printed circuit boards (PCB). They have finer lines and spaces (<75 µm), smaller vias (<150 µm) and capture pads (<400 µm), and higher connection pad density (>20 pads/cm2) than employed in conventional PCB technology. HDI is used to reduce size and weight, as well as to enhance electrical performance. In addition to HDI, terms such as "build-up board" in Japan and "sequential build-up (SBU)" or "microvia technology" in the U.S. can be used interchangeably.

With the migration to standards based interfaces the number of constraints on nets is also increasing. Particularly with DDRx standard there is not only an increase in the number of constraints on nets but there are a lot of additional constraints that are interdependent on each other. For example, for DDR2 memories all data signals in a byte lane must be matched in length and delay. Clocks must be longer than the lengths of Address, Command and Control signals at the same time length of all the clock signals must be between the longest Data Strobe signal and the shortest Data Strobe Signal. When customers who are designing with DDRx are forced to move to build-up technology for BGA fanouts, they require a system that can handle both the design requirements coming from such standards based interfaces and also from the build-up technology using HDI.

Many Cadence Allegro PCB users  have been doing blind and buried vias for a while now with the Constraint Driven Flow. They have been asking us to enhance the capabilities to make it easier to design PCBs with HDI.

Cadence have focused on this area to ensure that our customers continue to get the benefit of our proven Constraint Driven PCB design flow while working on HDI designs. It's not enough to do just HDI without a robust and comprehensive Constraint driven PCB design as a backbone.

With the migration to standards based interfaces the number of constraints on nets is also increasing. Particularly with DDRx standard there is not only an increase in the number of constraints on nets but there are a lot of additional constraints that are interdependent on each other. For example, for DDR2 memories all data signals in a byte lane must be matched in length and delay. Clocks must be longer than the lengths of Address, Command and Control signals at the same time length of all the clock signals must be between the longest Data Strobe signal and the shortest Data Strobe Signal. When customers who are designing with DDRx are forced to move to build-up technology for BGA fanouts, they require a system that can handle both the design requirements coming from such standards based interfaces and also from the build-up technology using HDI.

Many Cadence Allegro PCB users  have been doing blind and buried vias for a while now with the Constraint Driven Flow. They have been asking us to enhance the capabilities to make it easier to design PCBs with HDI.

Cadence have focused on this area to ensure that our customers continue to get the benefit of our proven Constraint Driven PCB design flow while working on HDI designs. It's not enough to do just HDI without a robust and comprehensive Constraint driven PCB design as a backbone.

As Part of the developemnt of an easy to use environment for build-up HDL Designs Cadence has added the following enhancements to Allegro PCB Editor for the 16.2 release: