LeCroy Summit T2-16 Protocol Analyzer

With advanced features such as support for PCI Express Spec 2.0, data rates of both 2.5 and 5 Gb/s, lane widths from x1 to x16, and a full 8 GB of trace memory, the Summit T2-16 provides unmatched capability and flexibility for developers and users of advanced PCI Express products. The Summit T2-16 is by far the most advanced and sophisticated PCI Express Analyzer available in the market today.

As with other LeCroy PCI Express analysers, the Summit T2-16 leverages the intuitive and powerful CATC Trace analysis software system, embedding a deep understanding of the PCI Express protocol hierarchy and intricacies. The colourful, intuitive and easy to use graphical display allows you to quickly capture and validate PCI Express product designs. All LeCroy PCI Express protocol analysers employ high-impedance, non-intrusive probing technology, thereby allowing fully unaltered data pass-through.

In addition to a full suite of advanced hardware and software features, the Summit T2-16 introduces new user-convenience and analysis features, such as support for “lane swizzling” which allows a board developer to lay out a mid-bus probe pad with lanes in non-standard order, simplifying the design of the board. Internally the PCTracer Gen2 Summit maps the lanes back into their correct order and accurately displays the embedded bus traffic. Other new software features include enhanced error checking for automatic identification of additional error types, more compact trace files that allow for faster analysis of trace data, and the choice of simplified or advanced modes for setting up trace recording options. A new raw recording mode allows bytes to be recorded as they come across the link, allowing debugging of PHY layer problems and combining the features of a logic analyzer format with a protocol analyzer format. The new auto sense link feature monitors negotiation between devices of different lane widths, and the bifurcated link support recombines multilink PCI Express operations that have been separated into narrower links.

The Summit T2-16 also introduces an Ethernet LAN port as a standard feature. By connecting over a LAN, engineers can operate the system remotely (e.g., install the client software on their desktop systems, and control an analyzer operating in a remote lab). Also, multiple engineers working collaboratively can time-share use of a single analyzer, reducing the need for an additional analyzer for each engineer, and increasing the cost effectiveness of the product.

The Summit T2-16 is available in two configurations—that support either x1, x2, x4, and x8; or x1, x2, x4, x8, and x16—to match user requirements with available budgets. The upward compatibility and 13 month warranty of the Summit T2-16 also provide investment protection for current Gen1 users who plan to upgrade to Gen2 devices in the future.

By leveraging years of experience in protocol analysis tools for emerging markets, LeCroy's PCI Express protocol analyses blend sophisticated functionality with practical features to speed the development of PCI Express IP cores, semiconductors, graphics, servers, workstations, bridges, and switches.

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Product Features

• Powerful and Intuitive CATC Trace Analysis Software System – The CATC Trace embeds deep understanding of the PCI Express protocol hierarchy and intricacies. This knowledge is presented in a colourful, intuitive, and easy-to-use graphical display, allowing you to quickly capture and validate PCI Express product designs.
• Lane-to-Lane Skew – Records and displays multi-lane links for faster analysis.
• Protocol Hierarchical Viewing – View Packet, Transaction, and Split Transaction levels of the PCI Express protocol; increased drill-down detail for PCI Express primitives, errors, payloads, or individual packets.
• Advanced Triggering – Allows you to trigger on various PCI Express Events such as Link Conditions, TLP Headers, DLLP Messages, Data Payload, etc.
• Lane-Reversal Compatible – Trigger, record, and display PCI Express traffic logically regardless of the physical configuration of the lanes.
• Statistical and Error Reporting – Provides you with a quick summary of the trace file to identify and track error rates, abnormal link, or timing conditions.
• Raw Recording Mode – Records the bytes exactly as they come across the link, allowing debugging of PHY layer problems.
• Auto Sense Lane Width – Analyses all negotiation traffic between devices with different lane widths, eliminating the need to set up lane widths before a trace.
• Lane Swizzling Support – Allows board developers to lay out lanes in a non-standard order, simplifying board design.
• Bifurcated Lane Support – Supports multilink operations where PCI Express ports are bifurcated into narrower links.
• Independent Power Supply – Record traces on systems during power up so that the full training sequences can be monitored accurately.
• Powerful Real-time BusEngine Protocol Processor Technology – Sophisticated triggering and filtering help focus on critical protocol data and isolate important protocol traffic, specific errors, or data patterns.
• Field-upgradeable Firmware and Engine – Positions you to receive the latest PETracer enhancements and future additional capabilities. Allows field upgrades from X8 to X16 systems.
• 8 GB Data Buffer – Capture long time windows for in-depth analysis and identification of erratic problems.
• 10/100 Mb/s Ethernet Connectivity – Allows connection to an Ethernet network and sharing of analyzer resources by multiple engineers.